1. Field of the Invention
This invention relates to computer systems, and more particularly, to methods and apparatus for providing a cache to hold data representing vertices of polygons being displayed by a computer graphics output device.
2. History of the Prior Art
In three dimensional graphics, surfaces are typically rendered by assembling a plurality of polygons in a desired shape. The polygons are conventionally triangles having vertices which are defined in world space by three dimensional coordinates, color values, texture coordinates, fog values, and other values. The three dimensional world space coordinates are translated into screen coordinates in which horizontal and vertical values define screen position and a depth value determines how near a vertex is to the screen and thus whether that vertex is viewed with respect to other points at the same screen coordinates. The color values define the brightness of each of red/green/blue colors at each vertex and thus the color at each vertex. The texture coordinates fix each vertex on a texture map, a matrix of values stored in memory which together describe a pattern to be applied to the surface of the triangle to vary the color values in accordance with the pattern.
The graphics accelerator utilizes the three dimensional coordinates received from the central processing unit to define the vertices of a triangle in screen space and from those to determine the individual pixels describing each triangle. For each pixel of the triangle, the graphics accelerator carries out a series of complex manipulations to determine the color values, depth values, texture coordinates, and other attributes in two dimensional screen space. Once these attributes are determined for a pixel, the accelerator uses the texture coordinates to generate a texture value for each pixel in another complex manipulation. Finally, all of the screen attributes of a pixel which affect the color of that pixel are combined to provide final color values for the pixel; and these pixel data are placed with the pixel address and depth in a rendering pipeline.
As may be appreciated, the amount of data required to define each vertex in an advanced three dimensional system is substantial. In one particular arrangement, thirty-two bytes of data are required to describe a single vertex. To accomplish the operations by which the individual pixels which describe the triangle are defined for use by some graphics output device, it is first necessary to transfer the data defining each vertex of each triangle from system memory to the graphics accelerator circuitry. Conventionally, data defining each individual vertex of a triangle is individually transferred by the central processing unit to the graphics accelerator over the system input/output (I/O) bus. This requires that the central processing unit use the bus control circuitry to gain access to the system (I/O) bus in order to transfer the data defining each of the vertices.
Twenty to forty bytes of data are typically required to define all of the attributes at each of the vertices in world space. In a computer with a thirty-two bit bus I/O bus, five to ten writes by the central processing unit are needed to transfer data describing a single vertex. On the other hand, a command may require less than a byte. Consequently, to transfer data defining three vertices and a command to render a triangle requires between sixteen and thirty-one bus transfers. If each transfer requires a bus acquisition, it may take from sixteen to thirty-one bus acquisitions to transfer the data describing a single triangle. Even when burst transfers are utilized, no more than a single vertex can be transferred in one burst so as many as four bus acquisitions are required to transfer the vertex data and a command to render a single triangle. Thus, both normal and burst transfers are relatively slow processes constrained by bus bandwidth and require a significant amount of central processor time.
It is desirable to transfer data for rendering polygons more rapidly between a source of graphics data and graphics accelerator circuitry in a manner which reduces the effect of bus bandwidth.